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Image of Test Generation of Crosstalk Delay Faults in VLSI Circuits

Electronic Resource

Test Generation of Crosstalk Delay Faults in VLSI Circuits

Jayanthy, S. - Personal Name; Bhuvaneswari, M.C. - Personal Name;

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This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.


Availability
Inventory Code Barcode Call Number Location Status
1908001959EB0002620621.395 JayCentral Library (OPAC)Available
Detail Information
Series Title
-
Call Number
621.395 Jay
Publisher
Singapore : Springer Singapore., 2018
Collation
XI, 156p.:ll
Language
English
ISBN/ISSN
978-981-13-2493-2
Classification
621.395
Content Type
Ebook
Media Type
-
Carrier Type
online resource
Edition
1
Subject(s)
Crosstalk
Specific Detail Info
-
Statement of Responsibility
BRF
Other version/related

No other version available

File Attachment
  • Test Generation of Crosstalk Delay Faults in VLSI Circuits
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