Electronic Resource

Design for Testability, Debug and Reliability

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Penilaian

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This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.

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Availability

Inventory Code	Barcode	Call Number	Location	Status
1908001054	EB0001660	621.381 5 Huh d	Central Library (OPAC)	Available

Detail Information

Series Title

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Call Number

621.381 5 Huh d

Publisher

Switzerland : Springer Cham., 2021

Collation

XXI, 164p.:Ill

Language

English

ISBN/ISSN

978-3-030-69209-4

Classification

621.381 5

Content Type

Ebook

Media Type

-

Carrier Type

online resource

Edition

1

Subject(s)

Integrated circuits--Design and construction

Specific Detail Info

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Statement of Responsibility

BRF

Other version/related

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