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Image of Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs

Electronic Resource

Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs

Zimpeck, Alexandra - Personal Name; Meinhardt,Cristina - Personal Name; Artola,Laurent - Personal Name; Reis, Ricardo - Personal Name;

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This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section.


Availability
Inventory Code Barcode Call Number Location Status
1908000972EB0001568621.381 528 4 MitCentral Library (OPAC)Available
Detail Information
Series Title
-
Call Number
621.381 528 4 Mit
Publisher
Switzerland : Springer Cham., 2021
Collation
XIII, 131p.:Ill
Language
English
ISBN/ISSN
978-3-030-68368-9
Classification
621.381 528 4
Content Type
Ebook
Media Type
-
Carrier Type
online resource
Edition
1
Subject(s)
Soft errors (Computer science)
Specific Detail Info
-
Statement of Responsibility
BRF
Other version/related

No other version available

File Attachment
  • Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs
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