Electronic Resource

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

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Penilaian

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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

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Availability

Inventory Code	Barcode	Call Number	Location	Status
1408000721	EB0003396	621.3815 Noi d	Central Library (Database Springer E-Book)	Available

Detail Information

Series Title

-

Call Number

621.3815 Noi d

Publisher

Switzerland : Springer Cham., 2013

Collation

xviii, 245p.: Ill.

Language

English

ISBN/ISSN

978-3-319-02378-6

Classification

621.3815

Content Type

Ebook

Media Type

-

Carrier Type

online resource

Edition

1

Subject(s)

Engineering

Specific Detail Info

-

Statement of Responsibility

RTS

Other version/related

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