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Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling

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This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

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Inventory Code Barcode Call Number Location Status
1408000622EB0003055621.381 Man sCentral Library (OPAC)Available
Detail Information
Series Title
-
Call Number
621.381 Man s
Publisher
New York : Springer New York, NY.,
Collation
xiii, 143.: Ill
Language
English
ISBN/ISSN
978-1-4614-9405-8
Classification
621.381
Content Type
Ebook
Media Type
-
Carrier Type
online resource
Edition
1
Subject(s)
Electronics
Specific Detail Info
-
Statement of Responsibility
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No other version available

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