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Image of Designing 2D and 3D Network-on-Chip Architectures

Electronic Resource

Designing 2D and 3D Network-on-Chip Architectures

Jantsch, Axel - Personal Name; Siozios, Kostas - Personal Name; Tatas, Konstantinos - Personal Name; Soudris, Dimitrios - Personal Name;

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This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.


Availability
Inventory Code Barcode Call Number Location Status
1408000512EB0002290006.22 Jan dCentral Library (OPAC)Available
Detail Information
Series Title
-
Call Number
006.22 Jan d
Publisher
New York : Springer New York, NY., 2013
Collation
xiii, 265p.: Ill.
Language
English
ISBN/ISSN
978-1-4614-4274-5
Classification
006.22
Content Type
Ebook
Media Type
-
Carrier Type
-
Edition
1
Subject(s)
Systems engineering
Specific Detail Info
-
Statement of Responsibility
RIZAL
Other version/related

No other version available

File Attachment
  • Designing 2D and 3D Network-on-Chip Architectures
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