Electronic Resource

ASIC Design and Synthesis

---

Penilaian

---

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

---

Availability

Inventory Code	Barcode	Call Number	Location	Status
1908001414	EB0002020	621.381 5 Tar a	Central Library (OPAC)	Available

Detail Information

Series Title

-

Call Number

621.381 5 Tar a

Publisher

Singapore : Springer Singapore., 2021

Collation

xxi, 330p.:Ill

Language

English

ISBN/ISSN

978-981-33-4642-0

Classification

621.381 5

Content Type

Ebook

Media Type

-

Carrier Type

online resource

Edition

1

Subject(s)

logic design

Specific Detail Info

-

Statement of Responsibility

BRF

Other version/related

File Attachment

Comments

---

You must be logged in to post a comment