Electronic Resource

Hardware Architectures for Post-Quantum Digital Signature Schemes

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Penilaian

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This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.

Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
Enables designers to build hardware implementations that are resilient to a variety of side-channels.

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Availability

Inventory Code	Barcode	Call Number	Location	Status
1908001379	EB0001985	621.381 5 Har	Central Library (OPAC)	Available

Detail Information

Series Title

-

Call Number

621.381 5 Har

Publisher

Switzerland : Springer Cham., 2020

Collation

xxii, 170p.:Ill

Language

English

ISBN/ISSN

978-3-030-57682-0

Classification

621.381 5

Content Type

Ebook

Media Type

-

Carrier Type

online resource

Edition

1

Subject(s)

Microprocessors

Specific Detail Info

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Statement of Responsibility

BRF

Other version/related

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