Electronic Resource

Synthesizable VHDL Design for FPGAs

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Penilaian

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The methodology described in this book is the result of many years of research experience in the field of synthesizable VHDL design targeting FPGA based platforms. VHDL was first conceived as a documentation language for ASIC designs. Afterwards, the language was used for the behavioral simulation of ASICs, and also as a design input for synthesis tools. VHDL is a rich language, but just a small subset of it can be used to write synthesizable code, from which a physical circuit can be obtained. Usually VHDL books describe both, synthesis and simulation aspects of the language, but in this book the reader is conducted just through the features acceptable by synthesis tools. The book introduces the subjects in a gradual and concise way, providing just enough information for the reader to develop their synthesizable digital systems in VHDL. The examples in the book were planned targeting an FPGA platform widely used around the world.

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Availability

Inventory Code	Barcode	Call Number	Location	Status
1408000287	EB0000495	005.71 Bez s	Central Library	Available

Detail Information

Series Title

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Call Number

005.71 Bez s

Publisher

Switzerland : Springer Cham., 2013

Collation

vii, 157p.: Ill.

Language

English

ISBN/ISSN

978-3-319-02547-6

Classification

005.71

Content Type

Ebook

Media Type

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Carrier Type

online resource

Edition

1

Subject(s)

Systems engineering

Specific Detail Info

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Statement of Responsibility

RTS

Other version/related

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