APA Style
Bezerra, Eduardo Augusto, Lettnin, Djones Vinicius. (2013).
Synthesizable VHDL Design for FPGAs (1).
Switzerland:
Springer Cham.
Chicago Style
Bezerra, Eduardo Augusto, Lettnin, Djones Vinicius.
Synthesizable VHDL Design for FPGAs.
1
Switzerland:
Springer Cham,
2013.
Electronic Resource.
MLA Style
Bezerra, Eduardo Augusto, Lettnin, Djones Vinicius.
Synthesizable VHDL Design for FPGAs.
1
Switzerland:
Springer Cham,
2013.
Electronic Resource.
Turabian Style
Bezerra, Eduardo Augusto, Lettnin, Djones Vinicius.
Synthesizable VHDL Design for FPGAs.
1
Switzerland:
Springer Cham,
2013.
Electronic Resource.